Computer product, apparatus, and method for supporting design

ABSTRACT

A computer-readable, non-transitory medium stores therein a design support program that causes a computer capable of accessing a storage device storing therein for each cell, an output voltage value of the cell, for each elapsed time period from a start of variation of an input voltage applied to the cell, to execute a process. The process includes extracting from the storage device, the output voltage value for each elapsed time period related to an cell under design selected from circuit information of a circuit under design; determining based on a specific voltage value, an extracted elapsed time period to be corrected; adding a time constant of an output from the cell under design to the elapsed time period determined to correction; and outputting the output voltage value for each corrected elapsed time period and the output voltage value for each elapsed time period that is not determined for correction.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority of theprior Japanese Patent Application No. 2010-139637, filed on Jun. 18,2010, the entire contents of which are incorporated herein by reference.

FIELD

The embodiments discussed herein are related to supporting design of asemiconductor integrated circuit.

BACKGROUND

In the design of an analog circuit, techniques of simulating an analogproperty using a simulator such as SPICE are conventionally known.

Meanwhile, in the design of a digital circuit, an accurate delay timeperiod can also be acquired by executing a simulation using a simulatorsuch as SPICE (see, e.g., International Patent Publication No.2004-501438) (hereinafter, “first conventional technique”). However,with techniques such as the first conventional technique, a problemarises in that a tremendous amount of time is necessary to execute asimulation for each cell in a circuit under design.

A technique is known of identifying a delay time period and anoutput-through (a time period necessary for an output voltage output bya cell to rise (or fall)), for each cell used in design employing asimulator such as SPICE, and storing the delay time period and theoutput-through as a library. The delay time period of each cell in thecircuit under design is calculated by referring to the library (see,e.g., Japanese Laid-Open Patent Publication No. H10-198720)(hereinafter, “second conventional technique”).

It is known that the delay time period of a path in a circuit underdesign is calculated by totaling delay time periods of cells thatconstitute the path.

However, with the second conventional technique, load resistance (suchas, for example, wiring resistance) and load capacitance (such as wiringcapacitance, and an input capacitance for a downstream cell) of theoutput of each cell are substituted by lumped constant capacitance, andtemporal variation of an output voltage is calculated using SPICE bysupplying temporal variation of an input voltage to a circuit model.

The values of the load resistance and the load capacitance differ amongcells depending on the layout of the circuit under design and therefore,a problem arises in that an error occurs for the delay time periodcompared to the case where the first conventional technique is used. Inaddition, the output voltage value is calculated using only the value ofthe lumped constant capacitance and therefore, the transient response byR (load resistance) and C (load capacitance) is approximated to astraight line. Therefore, another problem arises in that another erroris generated for the delay time period compared to the case where thefirst conventional technique is used. In addition, when the firstconventional technique is used, the above problem of a tremendous amountof time being consumed arises.

When the second conventional technique is used especially in recentprocessing enabling smaller dimensions, error between the delay timeperiods acquired by the first and the second conventional techniquesbecomes conspicuous with the lower voltage, the higher integration, andthe higher speed. Therefore, another problem arises in that the effectsof error in the delay time period can no longer be disregarded.

SUMMARY

According to an aspect of an embodiment, a computer-readable,non-transitory medium stores therein a design support program thatcauses a computer capable of accessing a storage device storing thereinfor each cell, an output voltage value of the cell, for each elapsedtime period from a start of variation of an input voltage applied to thecell, to execute a process. The process includes extracting from thestorage device, the output voltage value for each elapsed time periodrelated to an cell under design selected from circuit information of acircuit under design; determining, from among the extracted elapsed timeperiods and based on a specific voltage value, an elapsed time period tobe corrected; correcting by adding a time constant of an output from thecell under design to the elapsed time period determined at thedetermining; and outputting the output voltage value for each elapsedtime period corrected at the correcting and the output voltage value foreach elapsed time period that is not determined at the determining.

The object and advantages of the invention will be realized and attainedby means of the elements and combinations particularly pointed out inthe claims.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary and explanatory and arenot restrictive of the invention, as claimed.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is an explanatory diagram of an example of the present invention.

FIG. 2 is a block diagram of a hardware configuration of a designsupport apparatus according to embodiments.

FIG. 3 is a functional block diagram of the design support apparatusaccording to a first embodiment.

FIG. 4 is an explanatory diagram of an example of “process, temperature,and voltage” (PTV) conditions.

FIG. 5 is an explanatory diagram of an example of a cell.

FIG. 6 is an explanatory diagram of an example of “Vin”.

FIG. 7 is an explanatory diagram of a transistor property table.

FIG. 8 is an explanatory diagram of an example of Vds.

FIG. 9 is an explanatory diagram of an example of Ids for each Vds.

FIG. 10 is an explanatory diagram of Ids for each elapsed time period.

FIG. 11 is an explanatory diagram of a calculation result of rDS.

FIG. 12 is an explanatory diagram of another example of Vin.

FIG. 13 is an explanatory diagram of an exemplary reflection of an inputthrough.

FIGS. 14 and 15 are flowcharts of an example of a process procedure fordesign support by the design support apparatus according to the firstembodiment.

FIG. 16 is a functional block diagram of a design support apparatusaccording to a second embodiment.

FIG. 17 is an explanatory diagram of an example of an electric-currenttable group.

FIG. 18 is an explanatory diagram of an example of an internalresistance table group.

FIG. 19 is an explanatory diagram of an example of circuit informationof a circuit under design.

FIG. 20 is an explanatory diagram of an example of a wiring table.

FIG. 21 is an explanatory diagram of an example of input capacitance ofa cell.

FIG. 22 is an explanatory diagram of an example of a constraint table.

FIG. 23 is an explanatory diagram of an example of a threshold table.

FIG. 24 is an explanatory diagram of exemplary calculation of outputvoltage.

FIG. 25 is an explanatory diagram of exemplary determination of anelapsed time period to be corrected.

FIG. 26 is an explanatory diagram of exemplary correction.

FIG. 27 is an explanatory diagram of a correction result.

FIG. 28 is an explanatory diagram of exemplary calculation of a delaytime period.

FIG. 29 is an explanatory diagram of exemplary calculation ofoutput-through.

FIG. 30 is an explanatory diagram of calculation of a delay time periodin a second example.

FIGS. 31 to 34 are flowcharts of an example of a process procedure for adesign support process by the design support apparatus according to thesecond embodiment.

DESCRIPTION OF EMBODIMENTS

Preferred embodiments of the present invention will be explained withreference to the accompanying drawings.

FIG. 1 is an explanatory diagram of an example of the present invention.An electric-current table group retains therein for each cell, values ofthe voltage output by the cell at the elapse of each time period fromthe time of the start of variation of an input voltage applied to thecell; and is stored in a storage device that is accessible by a designsupport apparatus. The output voltage value of the cell is a valuecalculated without taking into account the values of the load resistanceand the load capacitance of the output of the cell.

The design support apparatus extracts based on an cell under designselected from among circuit information for a circuit under design, avalue of the voltage at an elapse of a time period related to the cellunder design; and determines an elapsed time period for Vds (outputvoltage) that is Vds<Vgs (input voltage)−Vth (gate threshold voltage) asan elapsed time period to be corrected. The embodiments will bedescribed assuming that “Vin” is same as “Vgs”.

The design support apparatus adds a time constant of the output from thecell under design to the elapsed time period to be corrected andthereby, corrects the elapsed time period. The “time constant” is avalue that is calculated based on the values of the load resistance andthe load capacitance of the output of the cell under design. The designsupport apparatus outputs the value of the voltage output at the elapseof each corrected time period, and the value of the voltage output atthe elapse of each time period not determined as that to be correctedhas elapsed.

In the first embodiment, exemplary creation of the electric-currenttable of a cell used in the circuit under design will be described. Inthe second embodiment, exemplary calculation of the delay time period ofthe cell under design selected from the circuit information of thecircuit under design using the electric-current table created in thefirst embodiment will be described.

FIG. 2 is a block diagram of a hardware configuration of a designsupport apparatus according to the embodiments. As depicted in FIG. 2,the design support apparatus includes a central processing unit (CPU)201, a read-only memory (ROM) 202, a random access memory (RAM) 203, amagnetic disk drive 204, a magnetic disk 205, an optical disk drive 206,an optical disk 207, a display 208, an interface (I/F) 209, a keyboard210, a mouse 211, a scanner 212, and a printer 213, respectivelyconnected by a bus 200.

The CPU 201 governs overall control of the design support apparatus. TheROM 202 stores therein programs such as a boot program. The RAM 203 isused as a work area of the CPU 201. The magnetic disk drive 204, underthe control of the CPU 201, controls the reading and writing of datawith respect to the magnetic disk 205. The magnetic disk 205 storestherein data written under control of the magnetic disk drive 204.

The optical disk drive 206, under the control of the CPU 201, controlsthe reading and writing of data with respect to the optical disk 207.The optical disk 207 stores therein data written under control of theoptical disk drive 206, the data being read by a computer.

The display 208 displays, for example, data such as text, images,functional information, etc., in addition to a cursor, icons, and/ortool boxes. A cathode ray tube (CRT), a thin-film-transistor (TFT)liquid crystal display, a plasma display, etc., may be employed as thedisplay 208.

The I/F 209 is connected to a network 214 such as a local area network(LAN), a wide area network (WAN), and the Internet through acommunication line and is connected to other apparatuses through thenetwork 214. The I/F 209 administers an internal interface with thenetwork 214 and controls the input/output of data from/to externalapparatuses. For example, a modem or a LAN adaptor may be employed asthe I/F 209.

The keyboard 210 includes, for example, keys for inputting letters,numerals, and various instructions and performs the input of data.Alternatively, a touch-panel-type input pad or numeric keypad, etc. maybe adopted. The mouse 211 is used to move the cursor, select a region,or move and change the size of windows. A track ball or a joy stick maybe adopted provided each respectively has a function similar to apointing device.

The scanner 212 optically reads an image and takes in the image datainto the design support apparatus. The scanner 212 may have an opticalcharacter reader (OCR) function as well. The printer 213 prints imagedata and text data. The printer 213 may be, for example, a laser printeror an ink jet printer.

FIG. 3 is a functional block diagram of the design support apparatusaccording to the first embodiment. The design support apparatus 300includes an acquiring unit 301, a variation time period calculating unit302, an elapsed time period calculating unit 303, and a storing unit304. The CPU 201 loads therein a design support program having thefunctions (the acquiring unit 301 to the storing unit 304) and stored ina storage device such as the ROM 202, the RAM 203, the magnetic disk205, or the optical disk 207 depicted in FIG. 2. The CPU 201 executesprocesses coded in the design support program, whereby the functions arerealized.

The acquiring unit 301 acquires an output current value for each outputvoltage value, from the storage device that stores therein an outputcurrent value of a cell for each output voltage value of the cell, equalto or higher than a specific voltage value. The “specific voltage value”is, for example, a voltage value that is Vgs(Vin)−Vth.

The variation time period calculating unit 302 calculates a variationtime period during which the output current value varies from that forthe lowest voltage value among the output voltage values up to that forthe highest voltage value thereof, based on a value of the junctioncapacitance of a transistor in the cell, a value of the gate thresholdvoltage (Vth) of the cell, and the output current values acquired by theacquiring unit 301.

The elapsed time period calculating unit 303 calculates for each outputcurrent value and based on the variation time period calculated by thevariation time period calculating unit 302, the elapsed time period fromthe start of the variation of the input voltage applied to the cell.

The storing unit 304 stores to the storage device, the elapsed timeperiod calculated for each output current value, by the elapsed timeperiod calculating unit 303.

The acquiring unit 301 acquires an output current value for each outputvoltage value, from the storage device storing therein, for a cell,output current values for each output voltage value of the cell, lowerthan the specific voltage value. The specific voltage value is, forexample, a value obtained by Vgs(Vin)−Vth.

Based on a value of the junction capacitance of the transistor in thecell, a value of the input voltage of the cell, and the output currentvalue acquired by the acquiring unit 301, the variation time periodcalculating unit 302 calculates a variation time period during which theoutput current value varies from the lowest voltage value of the outputvoltage values up to the highest voltage value thereof.

The elapsed time period calculating unit 303 calculates for each outputcurrent value and based on the variation time period calculated by thevariation time period calculating unit 302, an elapsed time period fromthe start of the variation of the input voltage.

The storing unit 304 stores to the storage device, the elapsed timeperiod calculated for each output current value by the elapsed timeperiod calculating unit 303.

Based on the above, an example of the creation of an electric-currenttable of an inverter will be described in detail.

FIG. 4 is an explanatory diagram of an example of PTV conditions. A PTVcondition table 400 includes a PTV condition column 401, a processcolumn 402, a temperature column 403, and a voltage column 404. The PTVcondition column 401 indicates whether a condition is a TYP condition, aFAST condition, or a SLOW condition.

The conditions are as follows:

TYP Condition: a condition under which each cell operates at an ordinaryspeed;

FAST Condition: a condition under which each cell operates at thehighest speed; and

SLOW Condition: a condition under which each cell operates at the lowestspeed.

Under the TYP condition, the process column 402 indicates “TYP condition(standard condition)”, the temperature column 403 indicates “25° C.(ordinary temperature)”, and the voltage column 404 indicates “1.8 [V]”.Under the FAST condition, the process column 402 indicates “FASTcondition (high speed condition)”, the temperature column 403 indicates“−40° C. (low temperature)”, and the voltage column 404 indicates “2.0[V]”. Under the SLOW condition, the process column 402 indicates “SLOWcondition (low speed condition)”, the temperature column 403 indicates“120° C. (high temperature)”, and the voltage column 404 indicates “1.1[V]”. The PTV condition table 400 is stored in a storage device such asthe RAM 203, the magnetic disk 205, or the optical disk 207. Thenumerical values and the PTV conditions in the PTV condition table 400are merely an example.

FIG. 5 is an explanatory diagram of an example of a cell. In the firstembodiment, the cell will be described taking an example of a cell of aninverter. In FIG. 5, the cell of the inverter whose inverter name is“INVERTER 1” is represented by a transistor description. The INVERTER 1includes a P channel metaloxide semiconductor (PMOS) and an N channelmetaloxide semiconductor (NMOS). A time difference between the an inputvoltage (Vin) input into an IN terminal and an output voltage (Vds)output from an OUT terminal is a delay time period. “C” depicted in FIG.5 denotes junction capacitance (parasitic capacitance) in the INVERTER 1and is different from the load capacitance of the output of the INVERTER1.

“Vds”, “Vds_nonRC”, and “Vds_RC” used in the first and the secondembodiments will be described. Vds, Vds_nonRC, and Vds_RC each representoutput voltages that are output from the OUT terminal. “Vds” used in thefirst embodiment is an output voltage set by a user. “Vds_nonRC” used inthe second embodiment is an output voltage that is calculated from theelectric-current table created in the first embodiment. “Vds_RC” used inthe second embodiment is an output voltage that is acquired bycorrecting Vds_nonRC, based on the load resistance and the loadcapacitance.

The first embodiment will be described taking an example of a case wherethere is a variation in the rising edge of the input to the IN terminal.A rising edge delay time period and a falling edge delay time period aresymmetrical and therefore, an example of a case where there is avariation in the falling edge of the input to the IN terminal will notbe described. In the first embodiment, an output current (Ids) at theOUT terminal when there is a rising edge variation in the input to theIN terminal is calculated and the calculation result is converted into atable.

FIG. 6 is an explanatory diagram of an example of “Vin”. In the firstand the second embodiments, the start of the variation in Vin is set ast=0. In the first embodiment, Ids is acquired for each time period thathas elapsed since the start of the variation. When Vin is Vin=0.0 [V]before t=0, Vds=Vdd and when the input of Vin rises at t=0, the PMOSimmediately cuts off. Therefore, in this case, the description will begiven noting only the NMOS.

As commonly known, a saturation region and a non-saturation region thatare operational regions of a MOS are classified as follows.

Saturation Region: Vds≧Vgs−Vth

Non-Saturation Region (Linear Region): Vds<Vgs−Vth

Equation (1) to calculate the current (Ids) output by the MOS when theoperational region of the MOS is the saturation region and Equation (2)to calculate the current (Ids) output by the MOS when the operationalregion of the MOS is the non-saturation region are given as follows.

$\begin{matrix}{{Ids} = {\frac{1}{2}\mu \; 0{{Cox}\left( \frac{W}{L} \right)}\left( {{Vgs} - {Vth}} \right)^{2}}} & (1) \\{{Ids} = {\mu \; 0{{Cox}\left( \frac{W}{L} \right)}\left( {{\left( {{Vgs} - {Vth}} \right){Vds}} - {\frac{1}{2}{Vds}^{2}}} \right)}} & (2)\end{matrix}$

Equations (1) and (2) are stored in a storage device such as the RAM203, the magnetic disk 205, or the optical disk 207. Parameters are asfollows.

“μ” [cm̂2/(V×s)]: carrier mobility

“ε0” (Epsilon Zero) [F/cm]: vacuum dielectric constant

“εox” (Epsilon ox) [F/cm]: relative dielectric constant

“Tox” [m]: oxide film thickness

“Cox” [F]: gate capacitance

“W” [m]: gate width

“L” [m]: gate length

“C” [F]: junction capacitance (parasitic capacitance)

FIG. 7 is an explanatory diagram of a transistor property table. Thetransistor property table 700 includes tables 701 and 712. Thetransistor property table 700 is stored in a storage device such as themagnetic disk 205 or the optical disk 207.

The table 701 stores therein the parameters for each MOS in the INVERTER1 and includes a transistor column 702, a μ column 703, a Cox column704, an ε0 column 705, an εox column 706, a Tox column 707, a W/L column708, a W column 709, an L column 710, and a C column 711.

The transistor column 702 retains therein the type of each MOS in theINVERTER 1. The μ column 703 retains therein “μ”. The Cox column 704retains therein “Cox”. The ε0 column 705 retains therein “ε0”. The εoxcolumn 706 retains therein “εox”. The Tox column 707 retains therein“Tox”. The W column 709 retains therein “W”. The L column 710 retainstherein “L”. The C column 711 retains therein “C”.

The W/L column 708 retains therein a ratio of W retained in the W column709 to L retained in the L column 710. For example, “35.42E-06” retainedin the Cox column 704 indicates 35.42×10̂(−6). “̂” represents a power.

The table 712 includes a transistor column 713 and a Vth column 714. Thetransistor column 713 retains therein the type of each MOS in theINVERTER 1. The Vth column 714 stores therein Vth (gate thresholdvoltage) of each transistor in the INVERTER 1 for each PTV condition.

For example, the CPU 201 selects a specific PTV condition, from the PTVcondition table 400. Alternatively, for example, the CPU 201sequentially selects the PTV conditions, from the PTV condition table400. In the first embodiment, the TYP condition will be described as anexample, i.e., “Vdd” is 1.8 [V].

FIG. 8 is an explanatory diagram of an example of Vds. A table 800includes a Vds column 801 that retains therein Vds. As depicted in FIG.8, in the first embodiment, Vds varies from 1.8 to 0.0 [V] in steps of0.1-[V] and Ids is calculated using Equations (1) and (2). When Vds isbetween 1.8 and 1.5 [V], the operational region of the INVERTER 1 is thesaturation region and therefore, Ids is calculated using Equation (1).When Vds is between 1.4 and 0.0 [V], the operational region of theINVERTER 1 is non-saturation region and therefore, Ids is calculatedusing Equation (2).

For example, the CPU 201 acquires Equation (1), from the storage device;acquires the parameters in Equation (1), from the transistor propertytable 700; sets the parameters in Equation (1); and calculates Ids forthe operational region of the NMOS, the saturation region. In otherwords, Ids is calculated for Vds, which is between 1.8 and 1.5 [V]. Inthe saturation region, Ids has the same electric-current valueregardless of the value of Vds. The calculation result is stored to astorage device such as the RAM 203, the magnetic disk 205, or theoptical disk 207.

For example, the CPU 201 acquires Equation (2), from the storage device;acquires the parameters in Equation (2), from the transistor propertytable 700; sets the parameters in Equation (2); acquires Vds (1.4 to 0.0[V]) sequentially from the table 800; sets the acquired Vds in Equation(2); and calculates Ids in the non-saturation region, for each Vds (1.4to 0.0 [V]). The calculation result is stored to a storage device suchas the RAM 203, the magnetic disk 205, or the optical disk 207.

FIG. 9 is an explanatory diagram of an example of Ids for each Vds. Atable 900 presents Ids for each Vds and includes a Vds column 901 and anIds column 902. The Vds column 901 retains therein Vds and the Idscolumn 902 retains therein Ids for the Vds.

In a graph 903, the axis of abscissa represents Vds [V]; the axis ofordinate represents Ids [A]; the electric-current value is high when Vdsis high; and the electric-current value is low when Vds is low. Forexample, a point at which Vds is Vds=Vgs is referred to as “point A”, apoint at which Vds is Vds=Vgs−Vth is referred to as “point B”, a pointat which Vds is Vds=Vgs/2 is referred to as “point C”, and a point atwhich Vds is Vds=0 is referred to as “point D”.

In the first embodiment, time periods during which the output current ofthe INVERTER 1 varies from the point A to the point B is denoted by“tAB”; from the point B to the point C is denoted by “tBC”; and from thepoint C to the point D is denoted by “tCD”. The time period tAB iscalculated by using Equation (3) as follows from Equation (1).

$\begin{matrix}\begin{matrix}{{tAB} = \frac{{CVgs} - {C\left( {{Vgs} - {Vth}} \right)}}{Ids}} \\{= \frac{CVth}{\frac{1}{2}\mu \; 0{{Cox}\left( \frac{W}{L} \right)}\left( {{Vgs} - {Vth}} \right)^{2}}}\end{matrix} & (3)\end{matrix}$

The time period tBC will be described. The time integral of an electriccurrent is an electric charge and therefore, Equation (4) is obtainedfrom an equation to calculate Ids in the non-saturation region.

$\begin{matrix}{{{Ids} \cdot {dt}} = {{- C} \cdot {dVds}}} & (4) \\{{\frac{\mu \; 0{{Cox}\left( \frac{W}{L} \right)}}{2C}{dt}} = {\frac{1}{2\left( {{Vgs} - {Vth}} \right)} \cdot \frac{dVds}{\frac{{Vds}^{2}}{2\left( {{Vgs} - {Vth}} \right)} - {Vds}}}} & (5)\end{matrix}$

Because Equation (5) is derived from Equation (4), the left-hand side ofEquation (5) is integrated from zero to tBC and the right-hand sidethereof is integrated from Vgs−Vth to ½×Vgs and thereby, Equation (6) isobtained.

$\begin{matrix}{{tBC} = {\frac{C}{\mu \; 0{{Cox}\left( \frac{W}{L} \right)}\left( {{Vgs} - {Vth}} \right)}{\ln \left( \frac{{3{Vgs}} - {4{Vth}}}{Vgs} \right)}}} & (6)\end{matrix}$

Equations (3) and (6) are stored to a storage device such as the RAM203, the magnetic disk 205, or the optical disk 207.

For example, the CPU 201 acquires Equation (3), from the storage deviceusing the variation time period calculating unit 302; acquires theparameters in Equation (3), from the transistor property table 700; setsthe parameters in Equation (3); and calculates the time period tAB. Forexample, the CPU 201 acquires Equation (6), from the storage device,using the variation time period calculating unit 302; acquires theparameters in Equation (6), from the transistor property table 700; setsthe parameters in Equation (6); and calculates the time period tBC.

The calculation results are indicated below.

tAB:3.279535511146584E-12

tBC:5.17154782518248E-12

For example, the CPU 201 converts Ids for each Vds into Ids for eachelapsed time period, based on the time periods tAB and tBC calculated.

FIG. 10 is an explanatory diagram of Ids for each elapsed time period. Atime period that has elapsed from the start of variation of Vin isreferred to as “elapsed time period”. In the embodiment, tAB is avariation time period during which the output current value varies from1.8 to 1.5 [V] and therefore, the CPU 201 calculates, for example, asfollows, the elapsed time period for each Vds (or each Ids), using theelapsed time period calculating unit 303.

The elapsed time period [sec] when Vds is 1.8 [V]: 0

The elapsed time period [sec] when Vds is 1.7 [V]: tAB/3

The elapsed time period [sec] when Vds is 1.6 [V]: tAB/3+(the elapsedtime period for 1.7 [V])

The elapsed time period [sec] when Vds is 1.5 [V]: tAB/3+(the elapsedtime period for 1.6 [V])

tBC is a variation time period during which the output current valuevaries from 1.4 [V] to 0.9 [V] and therefore, the CPU 201 calculates,for example, as follows, the elapsed time period for each Vds (or eachIds).

The elapsed time period [sec] when Vds is 1.4 [V]: tBC/6+(the elapsedtime period for 1.5 [V])

The elapsed time period [sec] when Vds is 1.3 [V]: tBC/6+(the elapsedtime period for 1.4 [V])

The elapsed time period [sec] when Vds is 1.2 [V]: tBC/6+(the elapsedtime period for 1.3 [V])

The elapsed time period [sec] when Vds is 1.1 [V]: tBC/6+(the elapsedtime period for 1.2 [V])

The elapsed time period [sec] when Vds is 1.0 [V]: tBC/6+(the elapsedtime period for 1.1 [V])

The elapsed time period [sec] when Vds is 0.9 [V]: tBC/6+(the elapsedtime period for 1.0 [V])

An example of Ids for each elapsed time period is a table 1000. Thetable 1000 includes an elapsed time period column 1001 and an Ids column1002. The table 1000 retains therein an elapsed time period for each Idsfrom 1.8 to 0.9 [V].

Assuming that the resolution (TIME SCALE) is 0E-12 [sec], an example ofthe elapsed time period for each Ids is an electric-current table 1003.The electric-current table 1003 includes an elapsed time period column1004, an Ids column 1005, and a Vin column 1006. The Vin column 1006 isnot depicted in FIG. 10.

An input threshold or an output threshold for calculating the delay timeperiod is Vdd×50 [%], and is Vds (for Vdd that is Vdd=Vds)×50 [%] orless for a section from the point C to the point D. In theelectric-current table 1003, TIME SCALE is allocated following the stepsof Vds from the table 900 for the section from the point C to the pointD. Not limited hereto, the operational region of the section from thepoint C to the point D is the non-saturation region and therefore, forexample, a user may also create in advance a calculation equationsimilarly to the calculation for the section from the point B to thepoint C and also calculate tCD. The CPU 201 stores the electric-currenttable 1003 in a storage device such as the RAM 203, the magnetic disk205, or the optical disk 207, using the storing unit 304.

Calculation of an internal resistance (rDS) of the NMOS in the INVERTER1 will be described. For example, the CPU 201 calculates rDS by dividingVds by Ids.

FIG. 11 is an explanatory diagram of the calculation result of rDS. Forexample, the CPU 201 calculates rDS for each Vds by dividing Vds by Idscalculated for each Vds. In this case, rDS acquired when the Vds isVds=1.8 [V] is determined as the value of the internal resistance of theNMOS in the INVERTER 1. rDS is stored in a storage device such as theRAM 203, the magnetic disk 205, or the optical disk 207.

Creation of an electric-current table taking into account influences of“tr” and “tf” will be described. “tr” represents a time period necessaryfor a rising edge of the input voltage (Vin) to rise and “tf” representsa time period necessary for a falling edge of the input voltage (Vin) tofall.

FIG. 12 is an explanatory diagram of another example of Vin. A graph1200 presents two examples of the variation of Vin, variations 1 and 2.Variation 1 depicts Vin that rises without any delay similarly to Vindepicted in FIG. 6. In variation 1, tr is zero. On the other hand, invariation 2, a time period of 10E-12 [sec] is necessary for Vin to varyfrom 0.0 to Vdd [V]. In the variation 2, tr is 10E-12 [sec]. Reflectingthe tr in the electric-current table 1003 gives the following.

FIG. 13 is an explanatory diagram of an exemplary reflection of an inputthrough. In this case, for example, it is assumed that a delay timeperiod that depends on the input through is a part of tr for Vin toreach Vth. The delay time period depending on the input through is10E-12/1.8×0.36 (tr/Vdd×Vth)=2.0E-12 [sec]. For example, the CPU 201 cancreate an electric-current table 1300 by adding the delay time period of2.0E-12 to the electric-current table 1003.

The electric current table 1300 includes an elapsed time period column1301, an Ids column 1302, and a Vin column 1303. The elapsed time periodcolumn 1301 retains therein an elapsed time period. The Ids column 1302retains therein Ids. The Vin column 1303 retains therein Vin. The Vincolumn 1303 has a value set therein such that the Vin is 1.8 [V] whenthe elapsed time period is 10E-12 [sec].

For example, the CPU 201 outputs the electric-current tables 1003 and1300. The form of the output can be, for example, display on the display208, output to the printer 213 for printing, or transmission to anexternal apparatus by the I/F 209. The electric-current tables 1003 and1300 may be stored to a storage device such as the RAM 203, the magneticdisk 205, or the optical disk 207.

FIGS. 14 and 15 are flowcharts of an example of the process procedurefor the design support by the design support apparatus 300 according tothe first embodiment. The CPU 201 first acquires the parameters of thetransistor (step S1401), selects the specific PTV condition from amongthe PTV conditions (step S1402), and acquires Vth under the PTVcondition selected (step S1403).

The CPU 201 acquires the Vds values under the PTV condition selected(step S1404) and acquires Equation (1) for calculating Ids related tothe saturation region (step S1405). The CPU 201 substitutes theparameters acquired, for variables in Equation (1) and calculates Idsfor each Vds that is equal to or higher than the specific voltage valueamong the of Vds values (step SS1406). As described, the specificvoltage value is obtained by Vgs(Vin)−Vth.

The CPU 201 acquires Equation (2) to calculate Ids related to thenon-saturation region (step S1407). The CPU substitutes the parametersacquired, for variables in Equation (2) and calculates Ids for each Vdsthat is lower than the specific voltage value among the Vds values (stepS1408). The CPU 201 calculates the value of the internal resistancebased on Ids and Vds (step S1409) and outputs the value of the internalresistance (step S1410).

The CPU 201 acquires Equation (3) to calculate tAB (step S1411);substitutes the parameters acquired, for variables in Equation (3);calculates tAB (step S1412); and calculates the elapsed time period foreach output current value for Vds that is equal to or higher than thespecific voltage value, based on tAB calculated (step S1413).

The CPU 201 acquires Equation (6) to calculate tBC (step S1414);substitutes the parameters acquired, for variables in Equation (6);calculates tBC (step S1415), and calculates the elapsed time period ofeach output current value for Vds that is lower than the specificvoltage value, based on tBC calculated (step S1416).

The CPU 201 stores the elapsed time period calculated for each Ids (stepS1417) and the series of process steps comes to an end.

In the second embodiment, exemplary calculation will be described of adelay time period of the cell under design in the circuit information ofthe circuit under design, using the electric-current tables that arecreated in the first embodiment. The second embodiment includes the samehardware as that are described in the first embodiment and therefore,the hardware components are given the same reference numerals used inthe first embodiment and will not again be described.

FIG. 16 is a functional block diagram of a design support apparatusaccording to the second embodiment. The design support apparatus 1600includes an extracting unit 1601, a determining unit 1602, a correctingunit 1603, an output unit 1604, an identifying unit 1605, and acalculating unit 1606. The CPU 201 loads therein a design supportprogram having the functions (the extracting unit 1601 to thecalculating unit 1606) and stored in a storage device such as the ROM202, the RAM 203, the magnetic disk 205, or the optical disk 207depicted in FIG. 2. The CPU 201 executes processes coded in the designsupport program, whereby the functions are realized.

From the storage device that stores therein for each cell, the value ofthe voltage output from the cell at the elapse of each time period fromthe time of the start of the variation of the input voltage applied tothe cell, the extracting unit 1601 extracts based on the cell underdesign selected from the circuit information of the circuit underdesign, a value of the voltage output at the elapse of each time periodrelated to the cell under design.

From among the elapsed time periods for output voltage values that areextracted by the extracting unit 1601, the determining unit 1602determines an elapsed time period to be corrected, based on the specificvoltage value. The “specific voltage value” is the value acquired byVgs(Vin)−Vth.

The correcting unit 1603 adds a time constant of the output of the cellunder design to the elapsed time period that is determined by thedetermining unit 1602.

The output unit 1604 outputs an output voltage value for each elapsedtime period after correction by the correcting unit 1603 and an outputvoltage value for each elapsed time period that is not determined by thedetermining unit 1602.

The identifying unit 1605 identifies an elapsed time period for anoutput voltage value that is a threshold of the output voltage of thecell under design, from among the output voltage values output by theoutput unit 1604.

The calculating unit 1606 calculates the time difference between anelapsed time period from the start of the variation of the input voltageapplied to the cell under design until the input voltage reaches athreshold of the input voltage, and the elapsed time period that isidentified by the identifying unit 1605.

The identifying unit 1605 identifies an elapsed time period for anoutput voltage value that is the threshold of the input voltage of thedownstream cell of the cell under design, from among the output voltagevalues output by the output unit 1604.

The calculating unit 1606 calculates the time difference between anelapsed time period during which the input voltage reaches the thresholdof the input voltage, from the start of the variation of the inputvoltage applied to the cell under design, and the elapsed time periodthat is identified by the identifying unit 1605.

The embodiment will be described in detail based on the above.

FIG. 17 is an explanatory diagram of an example of the electric-currenttable group. An electric-current table group 1700 includes anelectric-current table for each cell. Taking an example of the INVERTER1, the electric-current table group 1700 includes electric-currenttables for cells such as the electric-current tables of the INVERTERs 1and 2. The electric-current table group of the INVERTER 1 includes a TYPcondition table group, a FAST condition table group, and a SLOWcondition table group. The TYP condition table group includes a risingedge input table and a falling edge input table.

The falling edge input table includes tables for tf time periods. Therising edge input table includes tables for tr time periods. The risingedge input table group includes, for example, the electric-currenttables 1003 and 1300 described in the first embodiment. Theelectric-current table group 1700 is stored in the RAM 203, the magneticdisk 205, or the optical disk 207.

FIG. 18 is an explanatory diagram of an example of an internalresistance table group. The internal resistance table group 1800 retainstherein for each cell, the value of an internal resistance of a MOS inthe cell. For example, an internal resistance table 1801 retains thereinthe values of the internal resistances of the NMOS and the PMOS of theINVERTER 1.

In the second embodiment, a table is calculated that includes an outputvoltage value for each elapsed time period of an cell under designselected from the circuit information of the circuit under design, basedon the table 1300 including the output current value for each elapsedtime period and the internal resistance table 1801. Not limited hereto,a user may create in advance a table including the output voltage valuefor each elapsed time period for each cell.

FIG. 19 is an explanatory diagram of an example of the circuitinformation of the circuit under design. Circuit information 1900 iselectronic data that includes connection information of cells in thecircuit under design and for example, is layout data of the circuitunder design or a net list of the circuit under design acquired afterthe logic synthesis. The circuit information 1900 includes cells C1 toC7.

An “instance name” is a specific name of each cell in the circuit underdesign. A “cell name” is a name to represent the type of cell. “Cells C1to C7” are instance names. “INVERTERs 1 and 2”, “2AND1” (an AND havingtwo inputs and one output), “BUFFERs 1 and 2”, and “FF 1” are cellnames.

For example, elements like the INVERTERs 1 and 2 are both inverters andemploy the same logic, but have differing performance. For example, thecells 1 and 7 each have a different instance name although each is theINVERTER 1. In the second embodiment, the cells C1 and C7 have the samecell name while the wiring from the output of each cell and thedownstream cell of the cell are different from that of each other andtherefore, the time constant of each cell is different from that of eachother, and the upstream cell of the cell is different from that eachother and therefore, the input through of each cell is different fromthat of each other. Therefore, different delay time periods arecalculated for the cells C1 and C7.

For example, the CPU 201 calculates a delay time period for each of thecells C1 to C5 on a path P, totals the delay time periods calculated andthereby, can calculate a delay time period of the path P. For example,the CPU 201 divides the path P into sub-paths for the cells, obtainingpaths P1 to P5 and calculates the delay time period of each sub-path.

A “path” is a set of a series of cells and nets from an input terminalto a macro (for example, Flip-Flop (FF)) or a set of a series of cellsand nets between macros (for example, FFs). Alternatively, a “path” is aset of a series of cells and nets from a macro to an output terminal.

The wiring from the output of the cell C1 is cline 1, that of the cellC2 is cline 2, that of the cell C3 is cline 3, that of the cell C4 iscline 4, and that of the cell C5 is cline 5. In a semiconductorintegrated circuit, the wiring is formed using a metal or polysiliconand therefore, as depicted in the cline 1 of FIG. 19, the wiring isrepresented by a resistance (wiring resistance) and capacitance (wiringcapacitance).

FIG. 20 is an explanatory diagram of an example of a wiring table. Awiring table 2000 retains therein values of the wiring resistance andthe wiring capacitance of the wiring from the output of each cell to theinput of a downstream cell in the circuit information 1900. The wiringtable 2000 includes a wiring column 2001, a wiring resistance column2002, and a wiring capacitance column 2003.

The wiring column 2001 retains therein the wiring name. The wiringresistance column 2002 retains therein the value of the wiringresistance. The wiring capacitance column 2003 retains therein the valueof the wiring capacitance. The wiring table 2000 is created by a designengineer, based on the wiring information extracted from the layout dataof the circuit under design.

Referring back to FIG. 19, for example, the downstream cell of the cellC1 is the cell C2. The input capacitance of the cell C2 is a part of theload capacitance of the output of the cell C1 (load capacitance of thecell C1). The “input capacitance of a cell” is, for example, gatecapacitance of a MOS in the cell.

FIG. 21 is an explanatory diagram of an example of the input capacitanceof a cell. An input capacitance table 2100 retains therein the value ofthe input capacitance of each cell. The input capacitance table 2100includes a cell name column 2101 and an input capacitance column 2102.For example, when the cell name retained in the cell name column 2101 is“INVERTER 1”, the input capacitance column 2100 retains therein “five[fF]”.

Referring back to FIG. 19, for example, the cell C7 has no downstreamcell and downstream therefrom is an output terminal. In this case, theload resistance and the load capacitance of the output of the cell C7are unknown and therefore, in the second embodiment, the values of anexternal load resistance and external load capacitance that are definedin advance by the user (the design engineer, or a verifying engineer)are used as the values of the load resistance and the load capacitanceof the cell C7.

The cell C1 has no upstream cell and upstream therefrom is the inputterminal. In this case, the input through is unknown and therefore, inthe second embodiment, an external input through defined in advance bythe user (the design engineer, or the verifying engineer) is used as theinput through of the cell C1.

FIG. 22 is an explanatory diagram of an example of a constraint table. Aconstraint table 2200 has stored therein an external input through andthe values of the external load capacitance and the external loadresistance. In the second embodiment, as described above, the valueretained in an external input through column 2201 in the constrainttable 2200 is used for the input through of the cell C1; and the valuesretained in an external load capacitance column 2202 and in an externalload resistance column 2203 in the constraint table 2200 are used forthe load capacitance and the load resistance of the cell C7.

FIG. 23 is an explanatory diagram of an example of a threshold table. Athreshold table 2300 retains therein the threshold of the input voltage(hereinafter, “input threshold”) and the threshold of the output voltage(hereinafter, “output threshold”) used when the delay time period iscalculated based on the temporal variation of the input voltage and thatof the output voltage. The threshold table 2300 includes a cell namecolumn 2301, an input threshold column 2302, and an output thresholdcolumn 2303.

The cell name column 2301 retains therein a cell name. The inputthreshold column 2302 retains therein the input threshold. The outputthreshold column 2303 retains therein the output threshold. Taking anexample of a case where the cell name column 2301 retains “DEFAULT”, theinput threshold is 50 [%] and the output threshold is 50 [%]. In thiscase, it is indicated that the time difference between the elapsed timeperiod for Vin that is Vdd×50 [%] and the elapsed time period for Vdsthat is Vds×50 [%] is the delay time period of the cell under design.

An example of a specific process will be described. In a first example,calculation of the delay time period and the input through will bedescribed. In a second example, a case will be described where thethreshold of the downstream cell of the cell under design is differentfrom the threshold of the cell under design.

In the first example, the CPU 201 selects from the circuit information1900, the cell C1 as the cell under design; acquires the value of theinput capacitance of the cell downstream from the cell C1 (cell C2), thevalue of the wiring capacitance of the cline 1 of the output of the cellC1, and the value of the wiring resistance of the cline 1; anddetermines whether a cell upstream from the cell C1 is present. Becausea cell upstream is not present, the CPU 201 acquires the value retainedin the external input through column 2201 in the constraint table 2200and determines this value as the input through of the cell C1.

The acquisition results are as follows.

Value of Input Capacitance of Cell Downstream from Cell C1 (Cell C2): 5[fF]

Value of Wiring Capacitance of “cline 1”: 5 [fF]

Value of Wiring Resistance of “cline 1”: 50 [Ω]

External Input Through: 10E-12 [sec]

The CPU 201 automatically selects the cell under design in the secondembodiment and therefore, the CPU 201 accesses the storage device andacquires the values of the wiring capacitance and the wiring resistance,and the external input through. Not limited hereto, for example, theuser may select a cell under design and input into the design supportapparatus 1600, the values of the wiring capacitance and the wiringresistance, and the external input through, whereby the CPU 201 receivesthe input.

For example, because the cell name of the cell C1 is “INVERTER 1”, theCPU 201 extracts using the extracting unit 1601, the electric-currenttable of the rising edge input or the falling edge input, from theelectric-current table of the INVERTER 1 based on the external inputthrough. Taking an example of the rising edge input in this case, theelectric-current table 1300 is acquired.

For example, the CPU 201 calculates the value of the load capacitance ofthe cell C1, based on the values of the input capacitance of the cell C2and the wiring capacitance of the cline 1.

The value of the load capacitance of the cell C1=the value of the inputcapacitance of the cell C2+the value of the wiring capacitance of thecline 1

=5.0E-15[F]+5.0E-15[F]

=10.0E-15[F]

For example, the CPU 201 calculates the time constant by multiplying thevalue of the load capacitance of the cell C1 by the value of the wiringresistance of the cline 1. The calculation result is as follows.

Time constant of the cell C1=the value of the load capacitance of thecell C1×the value of the wiring resistance of the cline 1

=10.0E-15[F]×50[Ω]

=0.5E-12 [sec]

FIG. 24 is an explanatory diagram of exemplary calculation of the outputvoltage. For example, the CPU 201 calculates the value of the outputvoltage for each elapsed time period, based on the electric-currenttable extracted and the internal resistance of the NMOS of the INVERTER1. A table 2400 is the calculation result. The table 2400 includes anelapsed time period column 2401, a Vds_nonRC column 2402, and a Vincolumn 2403. The table 2400 is stored to a storage device such as theRAM 203, the magnetic disk 205, or the optical disk 207.

The elapsed time period of Vds_nonRC for which the operational region ofthe INVERTER 1 is the saturation region is not corrected using the timeconstant, and the elapsed time period of Vds_nonRC for which theoperational region of the INVERTER 1 is the non-saturation region iscorrected using the time constant. In the second embodiment, when theoperational region is the saturation region, the output currentsufficiently flows and therefore, the effects of the load capacitanceand the load resistance of the cell C1 are small. Therefore, the elapsedtime period of Vds_nonRC for which the operational region is thesaturation region is not corrected.

For example, the CPU 201 calculates Vgs(Vin)−Vth for each Vds_nonRC,using the determining unit 1602; and determines whether the Vds_nonRC isVds_nonRC<Vgs(Vin)−Vth, for each Vds_nonRC, using the determining unit1602. For example, the CPU 201 determines, using the determining unit1602, the elapsed time period of the Vds_nonRC as the elapsed timeperiod to be corrected when the Vds_nonRC is Vds_nonRC<Vgs(Vin)−Vth.

FIG. 25 is an explanatory diagram of exemplary determination of theelapsed time period to be corrected. For example, when the elapsed timeperiod is 10E-12 [sec], the Vds_nonRC is about 1.51 [V] and Vgs−Vth is1.44 [V]. Therefore, the Vds_nonRC is Vds_nonRC≧Vgs−Vth. Consequently,when the elapsed time period is 10E-12 [sec], the operational region ofthe NMOS of the INVERTER 1 is the saturation region.

For example, when the elapsed time period is 11E-12 [sec], the Vds_nonRCis about 1.41 [V] and the Vgs−Vth is 1.44 [V]. Therefore, the Vds_nonRCis Vds_nonRC≧Vgs−Vth. Consequently, when the elapsed time period is11E-12 [sec], the operational region of the NMOS of the INVERTER 1 isthe non-saturation region. Therefore, the elapsed time period that is10E-12 is determined as the elapsed time period to be corrected. In thiscase, 11E-12 to 19E-12 [sec] are determined as the elapsed time periodsto be corrected.

FIG. 26 is an explanatory diagram of exemplary correction. For example,the CPU 201 corrects using the correcting unit 1603, the elapsed timeperiod to be corrected by adding the time constant of the cell C1calculated to each elapsed time period that is determined as the elapsedtime period to be corrected.

In FIG. 26, for example, though “t0” is not the elapsed time period tobe corrected, “t1” and “t2” are elapsed time periods to be corrected. Ina graph 2604, t1 and t2 are corrected by adding τ thereto. Thecorrection results for t1 and t2 are “t1′” and “t2′”, respectively. Forexample, the CPU 201 outputs using the output unit 1604, the value ofthe output voltage for each elapsed time period after correction and theoutput voltage value for each elapsed time period that is not determinedas the elapsed time period to be corrected.

The form of the output can be, for example, display on the display 208,output to the printer 213 for printing, or transmission to an externalapparatus by the I/F 209. The output voltage values may be stored to astorage device such as the RAM 203, the magnetic disk 205, or theoptical disk 207.

The output result can be a table 2600 that includes an elapsed timeperiod column 2601, a Vds_RC column 2602, and a Vin column 2603. Theelapsed time period column 2601 retains therein an elapsed time period.The Vds_RC column 2602 retains therein the Vds_RC. The Vin columnretains therein the Vin. As to the Vds_RC, the voltage value thereofdoes not vary from the Vds_nonRC though the elapsed time period thereofis corrected.

If the number of measurements (the number of elapsed time periods) arefew, the elapsed time periods for the output voltage values may becorrected. For example, the CPU 201 corrects the elapsed time periodsusing Equation (7) below by calculating the Vds_RC for an elapsed timeperiod (tZ) that is intermediate between one elapsed time period (tX)and the next elapsed time period (tY) of the one elapsed time period.

Vds _(—) RC(tZ)={Vds _(—) RC(tX)[V]−Vds _(—)RC(tY)[V]}/{tX[psec]−tY[psec]}×τ[psec]+Vds _(—) RC(tY)[V]  (7)

For example, the correction will be described taking an example of acase where the tA and the tB are as follows.

tX=13.5 [psec]

tY=12.5 [psec]

tZ=13 [psec]

Vds(tX)=1.162[V]

Vds(tY)=1.297[V]

τ=0.5 [psec]

Vds_RC(13)={1.297[V]−1.162[V]}/{13.5 [psec]−12.5 [psec]}×0.5[psec]+1.162[V]=1.229[V]

FIG. 27 is an explanatory diagram of the correction result. A table 2700is the correction result acquired by correcting the table 2700 usingEquation (7). The table 2700 includes an elapsed time period column2701, a Vds_RC column 2702, and a Vin column. In FIG. 27, the Vin columnis not depicted. The correction has been executed only for a sectionbetween 12.5 and 19.5 [psec] as an example.

Calculation of the delay time period of the cell under design will bedescribed. For example, the CPU 201 retrieves the input threshold andthe output threshold of the cell under design from the threshold table2300, based on the cell name. The cell name corresponding to “INVERTER1” is not present in the threshold table 2300 and therefore, thethreshold of DEFAULT is retrieved. The input threshold of DEFAULT is 50[%] and the output threshold thereof is 50 [%].

For example, the CPU 201 identifies using the identifying unit 1605, theelapsed time period for Vds_RC that is equal to the output threshold ofthe cell under design acquired from the table 2700, and the elapsed timeperiod for Vin that is equal to the input threshold of the cell underdesign acquired from the table 2700. For example, the CPU 201 calculatesusing the calculating unit 1606, the time difference between the elapsedtime period for the Vin identified and that for the Vds_RC identified asthe delay time period.

FIG. 28 is an explanatory diagram of exemplary calculation of the delaytime period. In a graph 2800, input voltage values for the elapsed timeperiods are plotted and a line is depicted that sequentially connectsthe plotted values in order of elapsed time period (input voltage line),and output voltage values for the elapsed time periods are plotted and aline is depicted that sequentially connects the plotted values in orderof elapsed time period (output voltage line). In the graph 2800, theaxis of abscissa represents the elapsed time period and the axis ofordinate represents the voltage.

The input threshold is 50 [%] and the output threshold is 50 [%]. Thetime difference between the elapsed time period corresponding to avoltage that is Vdd×50 [%] on the input voltage line and the elapsedtime period corresponding to a voltage that is Vdd×50 [%] on the outputvoltage line is the delay time period of the cell under design. Theinput and the output voltage lines each simply connect the plottedvalues sequentially in order of elapsed time period. However, notlimited hereto, for example, approximation such as linear approximationmay be executed.

Calculation of the output-through of the cell under design will bedescribed. The output-through of the cell under design is used as aninput through of the cell downstream from the cell under design. Forexample, the output-through of the falling edge output of the cell underdesign is used for calculation of the delay time period of the fallingedge input of the downstream cell, and the output-through of the risingedge output of the cell under design is used for calculation of thedelay time period of the rising edge input of the downstream cell.

In the second embodiment, for the falling edge output, theoutput-through is defined as the time difference between the elapsedtime period corresponding to a voltage that is Vdd×80 [%] and theelapsed time period corresponding to a voltage that is Vdd×20 [%] and,for the rising edge output, the output-through is defined as the timedifference between the elapsed time period corresponding to a voltagethat is Vdd×20 [%] and the elapsed time period corresponding to avoltage that is Vdd×80 [%].

For example, the CPU 201 identifies using the identifying unit 1605, theelapsed time periods for Vds_RC corresponding to the voltages that areVdd×80 [%] and Vdd×20 [%] from the table 2700, and calculates using thecalculating unit 1606, the time difference between the two elapsed timeperiods identified, as the output-through.

FIG. 29 is an explanatory diagram of exemplary calculation of theoutput-through. In a graph 2900, output voltage values for the elapsedtime periods are plotted and a line is depicted that sequentiallyconnects the plotted values in order of elapsed time period. In thegraph 2900, the axis of abscissa represents the elapsed time period andthe axis of ordinate represents the voltage.

The time difference between the elapsed time period for the voltage thatis Vdd×80 [%] and the elapsed time period for the voltage that is Vdd×20[%] is the output-through. For example, the CPU 201 outputs the delaytime period and the output-through calculated. The form of the outputcan be, for example, display on the display 208, output to the printer213 for printing, or transmission to an external apparatus by the I/F209. Another form of output may be an output for storage to a storagedevice such as the RAM 203, the magnetic disk 205, or the optical disk207.

A case will be described where the output threshold of the cell underdesign and the input threshold of the cell downstream from the cellunder design differ from each other. In a second example, the cell underdesign is the cell C4 in the circuit information 1900.

For example, the CPU 201 identifies the downstream cell of the cell C4,from the circuit information 1900. In this case, the cell C5 isidentified as the downstream cell. For example, the CPU 201 retrievesfrom the threshold table 2300 and based on the cell name, the inputthreshold of the cell under design, and retrieves from the thresholdtable 2300 and based on the cell name, the input threshold of thedownstream cell.

The cell name of the cell C4 is “BUFFER 1” and therefore, the inputthreshold of the cell C4 is 40 [%]. The cell name of the cell C5 is“BUFFER 2” and therefore, the input threshold of the cell C5 is 50 [%].

For example, the CPU 201 identifies using the identifying unit 1605, theelapsed time period for the Vds_RC having a value equal to the inputthreshold of the cell under design and the elapsed time period for theVin having a value equal to the input threshold of the downstream cell,and calculates using the calculating unit 1606, the time differencebetween the two elapsed time periods identified, as the delay timeperiod.

FIG. 30 is an explanatory diagram of calculation of the delay timeperiod in the second example. In a graph 3000, exemplary calculation ofthe delay time period in the second example is depicted. In the graphs3000 and 3001, the input of the cell C4, the output of the cell C4 (theinput of the cell C5), and the output of the cell C5 are depicted.

For the graph 3001, the output threshold of the BUFFER 1 in the table isused for calculating the delay time period of the cell C4. In the graph3001, a time period is present that is shared by the calculation of thedelay time periods of the cells C4 and C5 and this time period is adelay error.

On the other hand, in the graph 3000, the input threshold of the cell C5is used as the output threshold of the cell C4 for calculating the delaytime period of the cell C4 and therefore, the delay error does notoccur. The occurrence of the delay error can be prevented.

FIGS. 31 to 34 are flowcharts of an example of a process procedure for adesign support process by the design support apparatus 1600 according tothe second embodiment. The CPU 201 divides the path P into sub-pathsrespectively for each the cell that constitutes the path P in thecircuit information (step S3101), sets “i” to be i=1 (step S3102), anddetermines whether a sub-path Pi that is i-th from the head of the pathP is present (step S3103).

If the CPU 201 determines that the sub-path Pi that is i-th from thehead is present (step S3103: YES), the CPU 201 selects the cell on thesub-path Pi as the cell under design (step S3104). The CPU 201determines whether the cell under design is an external input cell,based on whether a cell upstream from the cell under design is present(step S3105).

If the CPU 201 determines that the cell under design is an externalinput cell (step S3105: YES), the CPU 201 sets the input through of thecell under design to be an external through condition (step S3106). Onthe other hand, if the CPU 201 determines that the cell under design isnot an external input cell (step S3105: NO), the CPU 201 sets the inputthrough of the cell under design to be the output-through of theupstream cell (step S3107).

After step S3106 or S3107, the CPU 201 determines whether the cell underdesign is an external output cell, based on whether a cell downstreamfrom the cell under design is present (step S3108). The “external outputcell” refers to a cell under design whose output is not connected to anyother cell, whose output is connected to an output terminal, or whoseoutput is to an external destination.

At step S3108, if the CPU 201 determines that the cell under design isan external output cell (step S3108: YES), the CPU 201 acquires thevalues of the external load capacitance and the load resistance for thecell under design (step S3109). The CPU 201 sets the value of the loadresistance of the cell under design to be the value of the external loadresistance (step S3110) and sets the value of the load capacitance ofthe cell under design to be the value of the external load capacitance(step S3111).

At step S3108, if the CPU 201 determines that the cell under design isnot an external output cell (step S3108: NO), the CPU 201 acquires thevalues of the wiring capacitance of the cell under design, the inputcapacitance of the downstream cell, and the wiring resistance of thecell under design (step S3112). The CPU 201 sets the value of the wiringresistance of the cell under design to be the value of the wiringresistance of the cell under design (step S3113) and sets the value ofthe load capacitance of the cell under design to be the value of thewiring capacitance of the cell under design+the value of the inputcapacitance of the downstream cell (step S3114).

After step S3111 or S3114, the CPU 201 sets “τ” to be the value of theload capacitance of the cell under design×the value of the loadresistance of the cell under design (step S3115), selects a certain PTVcondition from among the PTV conditions (step S3116), and acquires theelectric-current table and the ON-resistance value of the cell underdesign (step S3117).

The CPU 201 multiplies each output current value in the electric-currenttable acquired by the ON-resistance value acquired (step S3118),acquires the Vth of the cell under design, based on the PTV condition(step S3119), and determines whether any unselected elapsed time periodis present (step S3120). If the CPU 201 determines that an unselectedelapsed time periods is present (step S3120: YES), the CPU 201 selectsone elapsed time period from among the unselected elapsed time periods(step S3121).

The CPU 201 determines whether the output voltage value of the elapsedtime period selected is less than the input voltage value of the elapsedtime period selected-Vth (step S3122). If the CPU 201 determines thatthe output voltage value of the elapsed time period selected is lessthan the input voltage value of the elapsed time period selected-Vth(step S3122: YES), the CPU 201 determines the elapsed time periodselected as the elapsed time period to be corrected (step S3123) and theprocedure returns to step S3120. If the CPU 201 determines that theoutput voltage value of the elapsed time period selected is not lessthan the input voltage value of the elapsed time period selected-Vth(step S3122: NO), the procedure returns to step S3120.

If the CPU 201 determines at step S3120 that no unselected elapsed timeperiod is present (step S3120: NO), the CPU 201 corrects the elapsedtime period that is determined to be corrected by adding τ thereto (stepS3124) and outputs the output voltage value for each elapsed time periodafter correction and the output voltage value for each elapsed timeperiod that is not determined to be corrected (step S3125).

The CPU 201 determines whether a cell downstream from the cell underdesign is present (step S3126). If the CPU 201 determines that adownstream cell is present (step S3126: YES), the CPU 201 acquires theinput thresholds of the cell under design and the downstream cell (stepS3127) and identifies the elapsed time period for the output voltagevalue that is the input threshold of the downstream cell (step S3128).

On the other hand, if the CPU 201 determines at step S3126 that adownstream cell is not present (step S3126: NO), the CPU 201 acquiresthe input threshold and the output threshold of the cell under design(step S3129) and identifies the elapsed time period for the outputvoltage value that is the output threshold of the cell under design(step S3130).

After step S3128 or S3130, the CPU 201 identifies the elapsed timeperiod for the input voltage value that is the input threshold of thecell under design (step S3131), calculates the time difference betweenthe two elapsed time periods identified (step S3132), and outputs thecell under design and the time difference calculated correlating thecell under design with the time difference as the delay time periodthereof (step S3133).

In the flowchart, the delay time period of the path P is calculated andtherefore, when a cell downstream from the cell under design is present,the delay time period is calculated using the input threshold of thedownstream cell as the output threshold of the cell under design.Thereby, the delay error of the path P can be suppressed. If only thedelay time period of the cell under design is necessary, the outputthreshold of the cell under design may be acquired and the delay timeperiod may be calculated using the acquired value even if a celldownstream from the cell under design is present.

The CPU 201 identifies the elapsed time period for the output voltagevalue that is the threshold of the output-through (step S3134),calculates the output-through of the cell under design (step S3135),outputs the cell under design and the output-through correlating theseto each other (step S3136), and sets “i” to be i=i+1 (step S3137). Theprocedure returns to step S3103.

If the CPU 201 determines at step S3103 that the sub-path Pi that isi-th from the head is not present (step S3103: NO), the CPU 201calculates the delay time period of the path P by totaling the delaytime periods of the cells on the path P (step S3138) and outputs thepath P and the delay time period calculated correlating these with eachother (step S3139).

As described above, according to the embodiments, the time constant of R(load resistance) C (load capacitance) of the output of the cell underdesign is defined as the delay time period by which the variation of theoutput voltage is delayed due to charging and discharging of the RC. Thedelayed time period is added to the elapsed time period that has elapsedfrom the start of the variation of the input voltage applied to the cellunder design and thereby, the elapsed time period is corrected. Thereby,the transient response by the RC that differs depending on the cells inthe circuit under design is restored. The output voltage that is madesluggish by the RC can be restored and the delay error can besuppressed.

The delay time period of the cell under design is calculated based onthe output voltage value and the input voltage value for each elapsedtime period after the correction and thereby, a delay time period havinga small delay error can be automatically calculated.

If a cell downstream from the cell under design is present, the delaytime period is calculated using the threshold of the input voltage ofthe downstream cell as the threshold of the output voltage of the cellunder design and thereby, a delay time period having a small delay errorcan be automatically calculated. Therefore, an accurate delay timeperiod of the path can be calculated.

As described above, according to the embodiments, the variation timeperiod is calculated during which the output current value varies fromthat for the lowest voltage value among the output voltage values thatare equal to higher than the specific threshold to that for the highestvoltage value thereof. The elapsed time period from the start of thevariation of the input voltage applied to the cell is calculated basedon the variation time period for each output current value, and theelapsed time period for each output current value is stored to thestorage device. Thereby, a table including the output current values forelapsed time periods can easily be created. The table of the outputcurrent value can also be used for calculation of the delay time periodsand an analysis of the electric power.

As described above, according to the embodiments, the variation timeperiod is calculated during which the output current value varies fromthat for the lowest voltage value among the output voltage values thatare less than the specific threshold to that for the highest voltagevalue thereof. The elapsed time period from the start of the variationof the input voltage applied to the cell is calculated based on thevariation time period for each output current value, and the elapsedtime period for each output current value is stored to the storagedevice. Thereby, a table including the output current values for elapsedtime periods can easily be created. The table of the output currentvalue can also be used for calculation of the delay time periods and ananalysis of the electric power.

The design support method described in the first and the secondembodiments may be implemented by executing a prepared program on acomputer such as a personal computer and a workstation. The program isstored on a computer-readable, non-transitory medium such as a harddisk, a flexible disk, a CD-ROM, an MO, and a DVD, read out from therecording medium, and executed by the computer. The program may be atransmission medium that can be distributed through a network such asthe Internet.

According to the embodiments, an effect is achieved that the sluggishoutput voltage at the RC can be restored and the delay error can besuppressed.

All examples and conditional language recited herein are intended forpedagogical purposes to aid the reader in understanding the inventionand the concepts contributed by the inventor to furthering the art, andare to be construed as being without limitation to such specificallyrecited examples and conditions, nor does the organization of suchexamples in the specification relate to a showing of the superiority andinferiority of the invention. Although the embodiments of the presentinvention have been described in detail, it should be understood thatthe various changes, substitutions, and alterations could be made heretowithout departing from the spirit and scope of the invention.

1. A computer-readable, non-transitory medium storing therein a designsupport program that causes a computer capable of accessing a storagedevice storing therein for each cell, an output voltage value of thecell, for each elapsed time period from a start of variation of an inputvoltage applied to the cell, to execute a process comprising: extractingfrom the storage device, the output voltage value for each elapsed timeperiod related to an cell under design selected from circuit informationof a circuit under design; determining, from among the extracted elapsedtime periods and based on a specific voltage value, an elapsed timeperiod to be corrected; correcting by adding a time constant of anoutput from the cell under design to the elapsed time period determinedat the determining; and outputting the output voltage value for eachelapsed time period corrected at the correcting and the output voltagevalue for each elapsed time period that is not determined at thedetermining.
 2. The computer-readable, non-transitory medium accordingto claim 1, the process further comprising: identifying from among theoutput voltage values output at the outputting, an elapsed time periodfor the output voltage value that is a threshold of the output voltageof the cell under design; and calculating a time difference between anelapsed time period from the start of variation of the input voltageapplied to the cell under design until the input voltage reaches athreshold of the input voltage, and the elapsed time period identifiedat the identifying.
 3. The computer-readable, non-transitory mediumaccording to claim 1, the process further comprising: identifying fromamong the output voltage values output at the outputting, an elapsedtime period for the output voltage value that is a threshold of theinput voltage of a cell downstream from the cell under design; andcalculating a time difference between an elapsed time period from thestart of variation of the input voltage applied to the cell under designuntil the input voltage reaches a threshold of the input, voltage, andthe elapsed time period identified at the identifying.
 4. A designsupport apparatus comprising: an extracting unit that extracts an outputvoltage value for each elapsed time period related to an cell underdesign selected from circuit information of a circuit under design, theelapsed time periods being extracted based on the cell under design andfrom a storage device storing therein for each cell, an output voltagevalue of the cell, for each elapsed time period from a start ofvariation of an input voltage applied to the cell; a determining unitthat determines, from among the extracted elapsed time periods and basedon a specific voltage value, an elapsed time period to be corrected; acorrecting unit that adds a time constant of an output from the cellunder design to the elapsed time period determined by the determiningunit; and an output unit that outputs the output voltage value for eachelapsed time period corrected by the correcting unit and the outputvoltage value for each elapsed time period that is not determined by thedetermining unit.
 5. A design support method executed by a computercapable of accessing a storage device storing therein for each cell, anoutput voltage value of the cell, for each elapsed time period from astart of variation of an input voltage applied to the cell, the designsupport method comprising: extracting from the storage device, theoutput voltage value for each elapsed time period related to a cellunder design selected from circuit information of a circuit underdesign; determining, from among the extracted elapsed time periods andbased on a specific voltage value, an elapsed time period to becorrected; correcting by adding a time constant of an output from thecell under design to the elapsed time period determined at thedetermining; and outputting the output voltage value for each elapsedtime period corrected at the correcting and the output voltage value foreach elapsed time period that is not determined at the determining.